The present invention relates in general to semiconductor devices and, more particularly, to power field effect transistors.
Most power transistors are formed with vertical structures to achieve a high current capability and a low on resistance. For example, one type of power metal-oxide-semiconductor field effect transistor, referred to as a trench field effect transistor (FET), has a gate dielectric formed along a vertical sidewall of a trench etched in the top surface of a semiconductor substrate. A gate electrode within the trench controls a conduction channel formed adjacent to the sidewall. Current through the device is routed vertically from a source formed at the top surface through the conduction channel to a drain formed at the bottom surface of the substrate. Trench FETs occupy a smaller die area than planar FETs and therefore have a lower fabrication cost. A power trench FET typically is specified to supply from 0.5 amperes to more than one hundred amperes of current.
However, most existing trench FETs suffer from a high gate to source capacitance, which increases power dissipation by slowing down the device""s switching speed. Moreover, a circuit that drives the gate must supply a high current to charge the gate to source capacitance, which further dissipates power. If the gate electrode is recessed away from the top surface of the substrate to reduce the capacitance, the effective gate resistance increases, which slows down the switching speed and reduces the performance of the device.
Hence, there is a need for a power trench field effect transistor which operates with a low gate to source capacitance and a low gate resistance in order to achieve a high switching speed and low power dissipation.